With the proliferation of portable devices such as smart phones, tablets, ultra-books etc. there continues to be a need for efficient integrated power management circuits. For example, in the effort to increase the power density of DC-DC converters or to have more power in decreasing areas, higher power density converters have been implemented. However, with higher power density converters, parasitic elements have to be minimized to reduce power loss and improved reliability. Energy stored in parasitic elements can supply bondwire inductance cause ringing when high side transistors (e.g. MOSFET) are switched on/off, causing voltage stress on the transistors.
In electrical networks, an electronic or electrical component can have parasitic elements that are not desirable for the component's intended purpose. The parasitic elements can take the form of parasitic resistance, parasitic inductance or parasitic capacitance. In semiconductor devices, these parasitic elements can be generated from the electronic components, and/or the mounting board. The generated parasitic elements can affect operations and performance of the semiconductor device.
Component designers strive to minimize the effects of the generated parasitic elements but are unable to completely eliminate them. High voltage stress across switches and hard switching are some examples of main drawback of present technologies to avoid the generated parasitic elements.
FIG. 1A shows a prior art conventional DC-DC buck converter. Prior art solutions have included adding an external decoupling capacitor close to the supply PVIN; however this does not solve the problem of package bondwire inductance (˜1-3 nH), as represented by Lpackage.
Conventionally high voltage ringing at the drain of high side MOSFET is mitigated by switching the high-side slowly and/or choosing a higher voltage rated power MOSFET. Gradual switching of the power MOSFET increases current-voltage (IV) overlap loss during transition. However, higher voltage power MOSFETs require increased area. Therefore, conventional methods either reduce achievable power efficiency or increase area of the DC-DC.
As shown in FIG. 1A Lboard is inductance from PCB routings and Lpackage is inductance from package bondwire. During turn on of high side device (HSD), Lpackage/Lboard causes undershoots in PVIN while inductances build current and overshoots once inductances have built current. As represented by the waveforms of FIG. 1B, during a turn off event of HSD, PVIN overshoots until the energy in Lpackage/Lboard is discharged either through slow turn off of the HSD or parasitic resistances in the PVIN-PGND power loop.
Conventionally, the driver needs to be slowed down to reduce PVIN transients; however, this degrades power efficiency. Alternatives include the use of higher voltage rated power MOSFET that are capable to handle voltage overshoots during turn on and off events; however this alternative requires greater area and can affect performance. In addition, in such conventional approaches, the energy stored in Lpackage is lost. For example, if Vout=1V, 5 A load, Lpackage=2 nH, Fsw=4.4 MHz. The power lost is 110 mW or 2.2% of output power. This can be significant loss in low voltage (Vin: 2.7V-5.5V) high efficiency DC-DC converters.